Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design - Nurul Ezaila Alias; Afiq Hamzah; Michael Loong Peng Tan; Usman Ullah Sheikh; Munawar A. Riyadi (Proceeding of the Electrical Engineering Computer Science and Informatics, 2019)
The development of the nanotechnology leadsto the shrinking of the size of the transistors to nanometerregion. However, there are a lot of challenges due to sizescaling of the transistors such as short channel effects (SCEs)and threshold voltage roll-off issues. Fin-Type Field EffectTransistor (FinFET) is another alternative technology tosolve the issues of the conventional MOSFET and increasethe performance of the Static Random Access Memory(SRAM) circuit design. FinFET based SRAMs are faster andmore reliable which are often used as memory cache for highspeed operation. However, 6T SRAM cell suffers from accesstransistor sizing conflict resulting in a trade-off between readand write stability. This paper presents an investigation ofthe stability performance in retention, read and write modeof 22nm FinFET based 8T SRAM cell. The performancecomparison of 22nm FinFET based 6T and 8T SRAMs weremade. The simulation of the SRAM model are carried out inGTS Framework TCAD tool based on 22nm technology. In8T SRAM cell, two n-FinFETs are added to the conventional6T SRAM cell which will be controlled by the Read WordLine (RWL) to isolate the read and write operation path forbetter read stability. FinFET based 8T SRAM cell givesbetter performance in Static Noise Margin (SNM) and powerconsumption than 6T SRAM cells. The simulation resultsaffirms the proposed FinFET based 8T SRAM improvedread static noise margin by 166.67% and power consumptionby 76.13% as compared to the FinFET based 6T SRAM.