A novel reduced instruction set computer-communication processor design using field programmable gate array - Joseph Anthony Prathap; Sai Ramesh (International Journal of Reconfigurable and Embedded Systems (IJRES), 2023)
In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.