Vector synthesis of fault testing map for logic - Hahanov, Vladimir; Gharibi, Wajeb; Chumachenko, Svetlana; Litvinova, Eugenia (IAES International Journal of Robotics and Automation (IJRA), 2024)
Vector synthesis of fault testing (simulation) map for logic is proposed, which without simulation allows to determine of all faults detected on test sets, as well as determining test sets to detect specified faults. For synthesis, a superposition of smart data structures is used, containing: a deductive matrix D, as a derivative of the logical vector L, test truth table T, and fault truth table F. The deductive matrix is seen as the gene of functionality and base of fault simulation mechanism to solve all the problems of testing and verification. In the matrix synthesis, an axiom is used: all the mentioned tables are identical in shape to each other and always interact with each other convolutionally T⊕L⊕F=0. A universal deductive reversing converter “test-faults” and “faults-test” for logical functionalities of any dimension is proposed. Converter functions: fault simulation on test sets T→F and synthesis of test sets F→T to detect the specified faults. The converter can be used as a test generation and fault simulation service for IP-core system-on-chip (SoC) under the IEEE 1500 SECT standard. Based on the deductive matrix, a fault testing map for logic is built, where each test set is matched with the logic-detected faults of the input lines.