Implementing a very high-speed secure hash algorithm 3 accelerator based on PCI-express - Huynh, Huu-Thuan; Tran, Tuan-Kiet; Dang, Tan-Phat (International Journal of Reconfigurable and Embedded Systems (IJRES), 2025)
In this paper, a high-performance secure hash algorithm 3 (SHA-3) is proposed to handle massive amounts of data for applications such as edge computing, medical image encryption, and blockchain networks. This work not only focuses on the SHA-3 core as in previous works but also addresses the bottleneck phenomenon caused by transfer rates. Our proposed SHA-3 architecture serves as the hardware accelerator for personal computers (PC) connected via a peripheral component interconnect express (PCIe), enhancing data transfer rates between the host PC and dedicated computation components like SHA-3. Additionally, the throughput of the SHA-3 core is enhanced based on two different proposals for the KECCAK-f algorithm: re-scheduled and sub-pipelined architectures. The multiple KECCAK-f is applied to maximize data transfer throughput. Configurable buffer in/out (BIO) is introduced to support all SHA-3 modes, which is suitable for devices that handle various hashing applications. The proposed SHA-3 architectures are implemented and tested on DE10-Pro supporting Stratix 10 - 1SX280HU2F50E1VG and PCIe, achieving a throughput of up to 35.55 Gbps and 43.12 Gbps for multiple-re-scheduled-KECCAK-f-based SHA3 (MRS) and multiple-sub-pipelined-KECCAK-f-based SHA-3 (MSS), respectively.