FPGA implementation of artificial neural network for PUF modeling - Mispan, Mohd Syafiq; Ishak, Mohammad Haziq; Jidin, Aiman Zakwan; Mohd Nasir, Haslinah (International Journal of Reconfigurable and Embedded Systems (IJRES), 2025)
Field-programmable gate array (FPGA) is a prominent device in developing the internet of things (IoT) application since it offers parallel computation, power efficiency, and scalability. The identification and authentication of these FPGAbased IoT applications are crucial to secure the user-sensitive data transmitted over IoT networks. Physical unclonable function (PUF) technology provides a great capability to be used as device identification and authentication for FPGAbased IoT applications. Nevertheless, conventional PUF-based authentication suffers a huge overhead in storing the challenge-response pairs (CRPs) in the verifier’s database. Therefore, in this paper, the FPGA implementation of the Arbiter-PUF model using an artificial neural network (ANN) is presented. The PUF model can generate the CRPs on-the-fly upon the authentication request (i.e., by a prover) to the verifier and eliminates huge storage of CRPs database in the verifier. The architecture of ANN (i.e., Arbiter-PUF model) is designed in Xilinx system generator and subsequently converted into intellectual property (IP). Further, the IP is programmed in Xilinx Artix-7 FPGA with other peripherals for CRPs generation and validation. The findings show that the Arbiter-PUF model implementation on FPGA using the ANN technique achieves approximately 98% accuracy. The model consumes 12,196 look-up tables (LUTs) and 67 mW power in FPGA.