Fault tolerant design for 8-bit Dadda multiplier for neural network applications - Chandrasekharan, Raji; Prasad, Sarappadi Narasimha (International Journal of Electrical and Computer Engineering (IJECE), 2025)
As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications. Therefore, there is need to design a power efficient and fault free Dadda multiplier that can address these challenges without significantly increasing power consumption or hardware complexity. In this paper a solution involving a fault tolerant Dadda multiplier optimized for neural network applications is proposed. Because of its speed and efficiency when compared to other multipliers Dadda multiplier is used as the base architecture which is designed using carry select adder (CSA) in conjunction with binary to excess one converter to reduce power and complexity. To enhance fault tolerance, self-repairing full adder is used to implement the CSA. This allows the system to detect and correct errors, ensuring robust operation in the presence of transient faults. This combination achieves a power efficient, fault tolerant multiplier with a power consumption of 52.3 mW, reflecting a 3% reduction in power compared to existing designs.