Enhancing power quality through DVR systems with advanced PLL-based ANFIS-optimized PI controller - Saritha, M.; Sidram, M. H. (International Journal of Power Electronics and Drive Systems (IJPEDS), 2025)
This paper presents a novel approach that integrates an advanced PLL with an ANFIS-optimized PI DVR controller, effectively mitigating voltage sags, swells, and harmonics in accordance with the IEEE 519 (2014b) guidelines for power quality in specialized application systems. The designed hybrid DVR controllers are tested using the hardware-in-the-loop OPAL-RT 4200 real-time simulator powered by an FPGA Kintex unit using the RT-LAB platform. The testing encompasses various loading conditions, including both nominal (100%) and increased (110%) loads. Under nominal loading conditions, the PLL-ANFIS optimized PI DVR controller is able to maintain power quality within acceptable limits. However, when the loading is increased to 110%, controllers based on the PLL-ANFIS optimized PI DVR method fail to meet the required standards. In contrast, the CDSC PLL-ANFIS optimized PI and MDSC PLL-ANFIS-optimized PI controllers perform better, successfully meeting the required limits. However, this achievement comes with a higher computational load and increased costs compared to alternative methods. Given the higher accuracy required to meet the IEEE 519 (2014a) guidelines for specialized applications, these trade-offs are considered acceptable, especially for critical and sensitive applications like healthcare facilities, semiconductor manufacturing plants, and pharmaceutical industries, where maintaining high power quality is crucial.