High-performance approximate MAC multiplier using majority logic compressors for CNNs - Selvarasan Radhakrishnan; Sudhagar Govindhaswamy; Rasadurai Kumaravel (International Journal of Reconfigurable and Embedded Systems (IJRES), 2026)
This research presents an optimized multiple accumulate (MAC) unit multiplier design for efficient convolutional neural network (CNN) operations. This design mainly focuses on making the multiplier systems smaller by using approximate majority compressor methods instead of the usual and traditional approximate methods. The traditional approximate multiplier compressor techniques are leads to increases in logic size, critical path delay, and power consumption; however, the proposed research mitigates these problems and solves them with a novelty-based approach in the Dadda multiplier technique. The novelty of this approach is to reduce the number of stages in the multiplier design using 4:2, 5:2, and 7:2 compressors. This compressor is designed with an approximate method using majority logic; compared to this traditional method, the proposed majority approximate compressor method processed less error differences in multiplication output. The proposed approaches resulted in significant reductions in area, power, and delay relative to traditional multipliers. This research compared seven unique comparisons of MAC-based multiplier architecture, and it will have been developed in Verilog hardware description language (HDL) and synthesized on the Xilinx Vertex-5 FPGA, providing reductions of 58.4% in lookup table (LUT) and 76.2% in occupied slices, and proving less power consumption. This design is a highly suitable approach for real-time CNN and digital signal processing (DSP) applications.