Optimization of 14 nm double gate Bi-GFET for lower leakage current - Nur Hazwani Naili Mohd Nizam; Afifah Maheran Abdul Hamid; Fauziyah Salehuddin; Khairil Ezwan Kaharudin; Noor Faizah Zainul Abidin; Anis Suhaila Mohd Zain (TELKOMNIKA (Telecommunication Computing Electronics and Control), 2023)
In recent years, breakthroughs in electronics technology have resulted in upgrades in the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy contenders due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene FET with a high-k/metal gate is proposed, which is composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. It is simulated and modelled using silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools, as well as the Taguchi L9 orthogonal array (OA). The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters. While the VTH adjustment tilt angle and the S/D implant tilt angle have both been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap semiconductor (ITRS) 2013 target than before.