Optimizing Digital Multipliers: A Study on Booth Radix-4 and Vedic Algorithms for FPGA - Estananto Estananto; Iswahyudi Hidayat; Muhammad Putra Perdana Fahrudin; Putri Ghina Khusnul Fuadah (JST (Jurnal Sains dan Teknologi), 2026)
Conventional multipliers in digital systems still face major challenges in the form of high latency, which negatively impacts performance in computationally intensive applications such as digital signal processing (DSP) and artificial intelligence. In addition, limitations in hardware resource efficiency present a significant challenge in designing systems that are both fast and area-efficient. This study aims to analyze the performance of 8-bit multipliers based on the Booth Radix-4 and Vedic (Urdhva Tiryagbhyam) algorithms in terms of speed and resource efficiency. This research adopts a quantitative approach. The research subjects consist of three 8-bit digital multiplier architectures: Shift-and-Add (baseline), Booth Radix-4, and Vedic. Data were collected using a documentation technique with instruments in the form of post-synthesis reports generated by the software, which include parameters such as propagation delay and logic element (LE) utilization. Data analysis was conducted using quantitative comparative analysis. The results show that both advanced algorithms (Booth and Vedic) perform significantly faster than the conventional method. The Booth Radix-4 multiplier demonstrates the best performance, with the lowest delay of 8.114 ns and a resource usage of 139 LEs, while the Vedic multiplier exhibits a delay of 9.298 ns and the highest resource consumption of 219 LEs. The study concludes that the Booth Radix-4 algorithm is the most optimal choice for implementing an 8-bit multiplier, as it provides the best balance between high speed and moderate resource utilization. The implications of this research provide a valuable reference for digital system designers in selecting appropriate multiplier architectures based on application requirements.