Design and Analysis of CMOS and Adiabatic 1:16 Multiplexer and 16:1 Demultiplexer - K. Anitha; R. Jayachira (Institute of Advanced Engineering and Science, 2016)
Conventional CMOS is compared with two adiabatic logic styles namely Efficient Charge Recovery Logic (ECRL) and Improved Efficient Charge Recovery Logic (IECCRL). A 16:1 multiplexer and 1:16 demultiplexer using these design techniques are designed and results are compared based on their minimum/maximum power consumption and transistor count. The proposed schematics multiplexer and demultiplexer are simulated using Microwind2 and DSCH2 software.