An Empirical Evaluation of Topologies for Large Scale NoC - Mehdi Baboli; Nasir Shaikh Husin (Institute of Advanced Engineering and Science, 2014)
In the past decades, processing power has achieved considerable gains. Researchers proposed faster uniprocessors that are capable of improving the instruction level parallelism through out-of-order implementation for increasing the performance quality of the existing network-on-chip (NoC). Although, the reducing returns of the performance of uniprocessor architecture caused multiprocessors to be integrated on a chip. In this paper, we selected a famous popular NoC topology, i.e., mesh, and evaluated it in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms, number of buffer, and hotspot traffic models. We selected two size of NoC, 12×12 and 16×16, as large scale NoC. We investigated all characteristics and measured latency, maximum delay, and total energy by Noxim simulator. In this paper, we demonstrated that when the network size and number of buffer were large, no routing algorithm could contribute to improve network performance. This is because the routing algorithms had the same performance in the large scale NoCs and they could not solve problems alone. Therefore, for a large scale system, the topology has a major impact on the performance and cost of the network. http://dx.doi.org/10.11591/telkomnika.v12i12.6840