A synchronization technique for single-phase grid applications - Issam A. Smadi; Saher A. Albatran; Taher Q. Ababneh (Institute of Advanced Engineering and Science, 2022)
The utility grid disturbances like dc offset and harmonic components can severely affect the estimated variables from the phase-locked loop (PLL), resulting in poor performance of the system relying on it. Therefore, there is an emerging need for well-designed PLL algorithms ensuring robust response against different operating conditions. This paper proposes a simple single-phase PLL algorithm with inherent dc offset and specific harmonic orders rejection capability. Utilizing adaptive time-delay fictitious signal generation. A full mathematical model of the proposed PLL has been provided. The proposed PLL is compared with other filter-based single-phase PLLs, to validate its simplicity and excellent performance.