Architectural framework and register-transfer level design synthesis for cost-effective smart eyewear - Kashish Malhotra; Revathi M. S.; Uma B. V.; Ajay K. M. (Institute of Advanced Engineering and Science, 2023)
In today’s time more than 70% of the world’s population suffer from eye disnormalities leading to the usage of eyewear or spectacles. Integrating profound technologies with daily utilities could serve some of the issues improving and optimizing our lifestyle to the most. One such way is to infuse nanosized chip in eyewear i.e., powered spectacles or shades to detect the location of the spectacles whenever it is necessary. The nanosized chip proposed has features including self-designed Bluetooth operating digital circuit, timer logic, clock generation using astable multivibrator circuit, emergency button, beep alarm and impact sensor. The values of resistance and capacitace is calculated to be 18 K ohm and 47 uF to obtain 1 Hz frequency. An optimal pin placement arrangement is analyzed, and the timing waveform is simulated using Verilog as proof of logical working of the chip. 13 D flipflops have been calculated to refrain from eye related strains. This paper suggests a bottom-up approach and develops the architectural framework of the chip, its working flow, system on chip top-view, digital logic description of each block and its implementation using Verilog hardware description language (HDL). The complexity and computational cost of the designed chip is minimal thus being commercially viable.