Rekontruksi Pembelajaran Komunikasi Digital Modulasi QPSK dengan Rewiring Modicom 5/1 dan Modicom 5/2 - Pambudi, Wisnu Setyo; Setiawan, Rudi (Akademi Angkatan Udara, 2022)
Communication systems are very decisive in modern warfare, the use of long-range weapons without crew requires a long-distance communication system using digital modulation communication. One of the basics of digital modulation communication that is important is QPSK modulation, so the Department of Electronics develops learning by conducting research on QPSK modulation and demodulation by conducting research on series block systems built on Modicom 5/1 and Modicom 5/2. Modicom 5/1 consists of blocks, namely the separation of serial data into MSB and LSB data, Unipolar to bipolar converters, Modulator I and Modulator Q and the summation of the Op-Amp. The Modicom 5/2 consists of a QPSK detector, a two-order filter, a comparator and a decoder differential. The results of the study prove that serial data from modicom 3/1 is in the form of serial data (D0,D1,D2,D3,D4,D5) separated by MSB data separator blocks (D0,D2,D4) and LSB (D1,D3,D5), serial data MSB and LSB (unipolar data standard (0V/+5V)) are converted to bipolar standard digital data (-4V/+4V) by a unipolar to bipolar converter block system. Balance Modulator (IC 1496) with MSB signal input ( I ) on modulator 1 carrier frequency of 960kHz (∟0º) and 960 kHz (∟-180º) on modulator 2 is LSB (Q) will output data in the form of an analog sine signal with a frequency of 960 KHz with different phase according to carrier signal '0'=∟-90º or '1'=∟-270 . the sum of the Module I and Q signal modules into phase angles of 00(45º),10(135º),11(225º), 01 (315º). The QPSK detector by means of the information signal is generated 4 times, the phase is detected (IC PLL) then divided by 4 , phase difference angle as control switch signal I and Q to get signal I and signal Q . The I and Q signals are filtered by fourth order butterworth then the I and Q signal data as comparator inputs to get a logic 0 or 1. Data I and O as logic data (0/1) as MSB and LSB data are combined again into discrete serial data with blocks differential decoder by using the PISO register (parallel input serial output) using IC 17HC175.