Exploring distance-based wireless transceiver placements for wireless network-on-chip architecture with deterministic routing algorithms - Lit, Asrani; Suhaili, Shamsiah; Kipli, Kuryati; Sapawi, Rohana; Mahyan, Fariza (Institute of Advanced Engineering and Science, 2024)
Network-on-chip (NoC) technology is crucial for integrating multiple embed-ded computing cores onto a single chip. Consequently, this has led to the de-velopment of the wireless network-on-chip (WiNoC) concept, seen as a promis-ing strategy to overcome scalability issues in communication systems withinchips for future many-core architectures. This research analyses the impactof wireless transceiver subnet clustering on the hundred-core mesh-structuredWiNoC architecture. The study aims to examine the effects of distance-basedwireless transceiver placements on the transmission delay, network throughput,and energy consumption within a mesh wireless NoC architecture featuring ahundred cores, under specific routing strategies: X-Y, west-first, negative-first,and north-last. This research investigates the impact of positioning radio sub-nets at the farthest, farther, nearest, and closest positions within an architectureequipped with four wireless transceivers. The Noxim simulator was utilised tosimulate the analysed wireless transceiver placements within the hundred-coremesh-structured WiNoC designs, with the objective of validating the results.The architecture with the wireless transceivers positioned at midway proxim-ity (nearer and further) demonstrated the best performance, as evidenced by thelowest latencies for all evaluated deterministic routing algorithms, according tothe simulation outcomes.