Adaptive silicon synapse and CMOS neuron for neuromorphic VLSI computing - El-Khatib, Ziad; Moussa, Sherif; Kamalov, Firuz; Yagoub, Mustapha C. E. (Institute of Advanced Engineering and Science, 2025)
The design of a fully integrated adaptive modified complementary metal-oxide-semiconductor (CMOS) synapse circuit is presented. By using multiple-gated transistor configuration in the modified CMOS synapse an additional branch provide control where the synaptic output current time-constant is tuned. The effect of changing the multiple-gated transistor bias voltage from 0.25 to 0.45 V tunes the spiking output current exponential time-constant range by 200 ms as shown in simulation results. Moreover, a fully-integrated adaptive quadratic integrate-and-fire (QIF) CMOS neuron circuit is presented as well. A differential pair with variable capacitor integrator and a tunable schmitt trigger threshold detector circuit are integrated in the CMOS neuron that can be tuned varying its spiking frequency. The proposed adaptive quadratic integrate-and-fire (AQIF) neuron has the ability to adjust the spiking frequency without changing the input current. The simulation results show the proposed CMOS neuron circuit spiking frequency can be tuned from 58.4 to 312.5 Hz and its spiking period from 17.1 to 3.2 ms with tuning the bias voltage of variable capacitor integrator. Having a peak voltage Vpeak=0.95 V, a reset voltage Vreset=-0.75 V and a voltage threshold of 0.35 V with a membrane potential range of 1.5 V. The proposed CMOS neuron circuit is designed in 130 nm process with a supply voltage of 1.8 V and a total power dissipation of 1.8 mW.