Optimization of a level shifter integrated with a gate driver using TSMC 130 nm CMOS technology - Guissi, Hicham; Slaoui, Khadija (Institute of Advanced Engineering and Science, 2025)
Modern electronic systems increasingly operate across multiple voltage domains, necessitating robust and efficient level shifter (LS) circuits to ensure reliable inter-domain communication. In low-power digital applications, minimizing propagation delay and transition time is critical for achieving high-speed and energy-efficient operation. This work presents a high-performance level shifter optimized for integration within Li-ion battery charger systems. The proposed design achieves a substantial reduction in propagation delays from 0.15 to 0.09062 ns while preserving signal integrity. When integrated with a gate driver, the overall structure exhibits a propagation delay of 0.20468 ns and a transition time of 0.014 ns, marking a significant improvement from the previous 0.036 ns. Furthermore, the proposed circuit occupies only 0.00039 mm² of silicon area, representing a 92% reduction compared to prior implementations (0.05 mm²). The complete design was implemented using Taiwan semiconductor manufacturing company (TSMC) 130 nm complementary metal–oxide– semiconductor (CMOS) technology, with both schematic simulation and layout carried out in the Cadence Virtuoso design environment. These results underscore the potential of the proposed solution for compact and high-efficiency system-on-chip (SoC) battery management applications.