Faults detection in SOC using TCRMCN based MBIST with optimization based BISR - Madhava Rao Jillella; Prashanth Narayanappa Ananda (Institute of Advanced Engineering and Science, 2026)
Memory takes up much of the chip area in modern system on chip (SOC). It is more challenging to repair these memories with a traditional external equipment test method. In this paper, SOC devices using temporal channel reconfiguration multi-graph convolution networks (TCRMCN), based memory built-in self-test (MBIST), with optimization based built-in-self-repair (BISR) (TCRMCN-MBIST-BISR-SOC) is proposed. Further the results of the test are analyzed by TCRMCN, which detects different types of faults. Once faults are detected, the data is passed to BISR, where the faulty memory cells are replaced using redundant memory cells and optimized by multi-objective fitness dependent optimization algorithm (MOFDOA). The proposed method demonstrates significant improvements in delay, power consumption, and access time, outperforming existing approaches like adaptive dynamic k-nearest neighbor (ADKNN) fostered BIST and Namib beetle optimization approach (NBOA) espoused BISR for SOC-based devices (ADKNNF-BIST-NBOA-BISR), deep q-learning with bit-swapping-based linear feedback shift register fostered BIST and BISR for static random access memory (SRAM) (DQL-BSL-BIST-BISR), and design of a fast and energy-efficient MBIST architecture using Verilog (DFEC-MBIST), the proposed method achieves 9.28%, 8.78%, and 9.29% higher accuracy while reducing delay by 9.45%, 5.36%, and 8.28%, respectively.