A counter-centric binary-to-binary coded decimal and multiplexed seven-segment driver on an Artix-7 FPGA - Ahmed Mohamed Abdellatif Abdelrahman Elngar; Muhamad S. Mauladdawilah; Tariq H. M. Alomary (Universitas Ahmad Dahlan, 2026)
This paper presents a complete field-programmable gate array (FPGA) implementation for showing a 4-bit binary value (0–15) as a two-digit decimal number on the Nexys-4 double data rate (DDR) seven-segment display. The design comprises: (i) a compact binary-to-binary-coded decimal (BCD) converter tailored to the 0–15 range; (ii) a seven-segment decoder for active-low, common-anode digits; and (iii) a counter-based clock-enable controller that time-multiplexes the digits at a rate chosen to be flicker-free yet energy-efficient. A simple timing model links the divider width , the number of digits , and the refresh rate . Simulation verified hazard-free switching and one-hot anode selection; hardware tests on the Nexys-4 DDR (100 MHz clock) confirmed the analysis. Selecting yields ms and Hz, which removes ghosting while avoiding unnecessary high-frequency scanning. The system displays all inputs correctly and provides a clear sizing rule for wider inputs and more digits. The approach is fully synthesizable, resource-light, and portable to larger word-lengths and displays.