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Jung, Hakkee
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Computer Science & IT Electrical & Electronics Engineering

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Journal : International Journal of Electrical and Computer Engineering

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Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET Jung, Hakkee
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i1.pp232-239

Abstract

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs. The characteristics between the drain current and the gate voltage is derived by using the potential distribution model to propose in this paper. In this case, the threshold voltage is defined as the corresponding gate voltage when the drain current is (W/L) × 10-7 A, and the DIBL representing the change in the threshold voltage with respect to the drain voltage is obtained. As a result, we observe the DIBL is proportional to the negative third power of the channel length and the second power of the silicon thickness and linearly proportional to the geometric mean of the top and bottom gate oxide thicknesses, and derive a relation such as DIBL =25.15ηL_g^(-3) t_si^2 √(t_ox1∙t_ox2 ), where η is a static feedback coefficients between 0 and 1. The η is found to be between 0.5 and 1.0 in this model. The DIBL model of this paper has been observed to be in good agreement with the result of other paper, so it can be used in circuit simulation such as SPICE.
Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide Jung, Hakkee
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i1.pp240-248

Abstract

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.
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