Hiroki Tamura
University of Miyazaki

Published : 6 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 6 Documents
Search
Journal : International Journal of Electrical and Computer Engineering

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit Agung Setiabudi; Hiroki Tamura; Koichi Tanno
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (572.475 KB) | DOI: 10.11591/ijece.v8i6.pp4148-4156

Abstract

A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.
CMOS Temperature Sensor with Programmable Temperature Range for Biomedical Applications Agung Setiabudi; Hiroki Tamura; Koichi Tanno
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 2: April 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1626.699 KB) | DOI: 10.11591/ijece.v8i2.pp946-953

Abstract

A CMOS temperature sensor circuit with programmable temperature range is proposed for biomedical applications. The proposed circuit consists of temperature sensor core circuit and programmable temperature range digital interface circuit. Both circuits are able to be operated at 1.0 V. The proposed temperature sensor circuit is operated in weak inversion region of MOSFETs. The proposed digital interface circuit converts current into time using Current-to-Time Converter (ITC) and converts time to digital data using counter. Temperature range can be programmed by adjusting pulse width of the trigger and clock frequency of counter. The proposed circuit was simulated using HSPICE with 1P, 5M, 3-wells, 0.18-μm CMOS process (BSIM3v3.2, LEVEL53). From the simulation of proposed circuit, temperature range is programmed to be 0 °C to 100 °C, it is obtained that resolution of the proposed circuit is 0.392 °C with -0.89/+0.29 °C inaccuracy and the total power consumption is 22.3 μW in 25 °C. 
Simple Measurement System for Biological Signal Using a Smartphone Ryoichi Miyauchi; Koichi Tanno; Hiroki Tamura
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (713.397 KB) | DOI: 10.11591/ijece.v8i6.pp4157-4163

Abstract

This paper describes simple measurement system for biological signal using smartphone. The proposed system consists of an instrumentation amplifier, a filter and an AC/DC converter. The biological signal is converted to the digital data through the microphone terminal with A/D converter in the smartphone. In many cases, the circuits require the power sources such as the cell batteries, however, the proposed system is supplied the power through the earphone terminal of the smartphone. Therefore, the proposed system no require the batteries. The software of this system parallelizes the processing so that the earphone output and the microphone terminal can be executed at the same time. The proposed system was verified through the measurement of surface electromyogram using discrete parts and iOS. Results of experimentation, the proposed system was operating correctly.
Low Common-Mode Gain Instrumentation Amplifier Architecture Insensitive to Resistor Mismatches Zainul Abidin; Koichi Tanno; Shota Mago; Hiroki Tamura
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 6: December 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (397.404 KB) | DOI: 10.11591/ijece.v6i6.pp3247-3254

Abstract

In this paper, an instrumentation amplifier architecture for biological signal is proposed. First stage of conventional IA architecture was modified by using fully balanced differential difference amplifier and evaluated by using 1P 2M 0.6μm CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by proposed IA architecture. Actual fabrication was done and six chips were evaluated. From the evaluation result, average common-mode gain of proposed IA architecture is 10.84 dB lower than that of conventional one without requiring well-matched resistors. Therefore, the proposed IA architecture is suitable for biological signal processing.
Proposal and design methodology of switching mode low dropout regulator for Bio-medical applications Kenya Kondo; Hiroki Tamura; Koichi Tanno
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 6: December 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v9i6.pp5046-5059

Abstract

The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications.
New active diode with bulk regulation transistors and its application to integrated voltage rectifier circuit Ryoichi Miyauchi; Koichi Tanno; Hiroki Tamura
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 2: April 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (468.745 KB) | DOI: 10.11591/ijece.v9i2.pp902-908

Abstract

This paper describes new active diode with bulk regulation transistors and its application to the integrated voltage rectifier circuit for a biological signal measurement system with smartphone. The conventional active diode with BRT has the dead region which causes leak current, and the output voltages of the application (e.g. voltage rectifier circuit) decrease. In order to overcome these problem, we propose new active diode with BRT which uses the control signal from the comparator of active diode to eliminate the dead region. Next we apply the proposed active diode with BRT to the integrated voltage rectifier circuit. The proposed active diode with BRT and voltage rectifier circuit were fabricated using 0.6 μm standard CMOS process. From experimental results, the proposed active diode with BRT eliminates the dead region perfectly, and the proposed voltage rectifier circuit generates + 2.86 V (positive side) and - 2.70 V (negative side) under the condition that the amplitude and frequency of the input sinusoidal signal are 1.5 V and 10 kHz, respectively, and the load resistance is 10 kΩ.