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All Journal International Journal of Electrical and Computer Engineering
Fatima Zahrae Zenkouar
Sidi Mohammed Ben Abdellah University
Computer Science & IT Electrical & Electronics Engineering

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Journal : International Journal of Electrical and Computer Engineering

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GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm Fatima Zahrae Zenkouar; Mustapha El Alaoui; Said Najah
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 3: June 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i3.pp2184-2193

Abstract

This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the same time, it also provides a non-binary LDPC (NB-LDPC) code set program. Furthermore, the simplified bubble check treasure event count is implemented through the use of first in first out (FIFO), which is based on an elegant design. The structure of the interpreter and the creation of the residential area he built were planned in very high speed integrated circuit (VHSIC) hardware description language (VHDL) and simulated in MODELSIM 6.5. The combined output of the Cyclone II FPGA is combined with the simulation output.
Co-Authors Mustapha El Alaoui Said Najah