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Gurmohan Singh
Centre for Development of Advanced Computing (C-DAC)
Computer Science & IT Electrical & Electronics Engineering

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Journal : International Journal of Electrical and Computer Engineering

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A Novel Low Noise High Gain CMOS Instrumentation Amplifier for Biomedical Applications Akshay Goel; Gurmohan Singh
International Journal of Electrical and Computer Engineering (IJECE) Vol 3, No 4: August 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

This work describes a novel technique of designing a low noise high gain CMOS instrumentation amplifier for biomedical applications. A three op-amp instrumentation amplifier have been designed by employing two simple op-amps at the two inputs and a folded cascode op-amp at the output. Both input and output stage op-amps are 2-stage. Most of the earlier designed op-amp in literature uses same type of op-amp at the input and output stages of instrumentation amplifier. By using folded cascode two stage op-amp at the output, we have achieved significant improvement in gain and CMRR. Transistors sizing plays a vital role in achieving high gain and CMRR. To achieve a desirable gain, common mode rejection ratio and other performance metrics, selection of most appropriate op-amp circuit topologies & optimum transistor sizing was the main criteria for design of instrumentation amplifier for biomedical applications. The instrumentation amplifier is simulated using Cadence Spectre tool and layout is designed in Cadence Layout editor at 0.18µm CMOS technology. Each of the input op-amp provides a gain and CMRR of 45dB and 72dB respectively. The output stage folded cascode amplifier provides a gain of 82dB and a CMRR of 92dB. The design achieves an overall gain and CMRR of 67dB and 92db respectively. The designed instrumentation amplifier consumes only 263µW of power suitable for biomedical signal processing applications.DOI:http://dx.doi.org/10.11591/ijece.v3i4.3170
Co-Authors Akshay Goel