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Neeta Pandey
Delhi Technological University, India
Computer Science & IT Electrical & Electronics Engineering

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Journal : International Journal of Electrical and Computer Engineering

 1 
New Realization of Quadrature Oscillator using OTRA Gurumurthy Komanaplli; Neeta Pandey; Rajeshwari Pandey
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (396.06 KB) | DOI: 10.11591/ijece.v7i4.pp1815-1823

Abstract

In this paper a new, operational transresistance amplifier (OTRA) based, third order quadrature oscillator (QO) is presented. The proposed structure forms a closed loop using a high pass filter and differentiator. All the resistors employed in the circuit can be implemented using matched transistors operating in linear region thereby making the proposed structure fully integrated and electronically tunable. The effect of non-idealities of OTRA has been analyzed which suggests that for high frequency applications self-compensation can be used. Workability of the proposed QO is verified through SPICE simulations using 0.18μm AGILENT CMOS process parameters. Total harmonic distortion (THD) for the proposed QO is found to be less than 2.5%.The sensitivity, phasenoise analysis is also discussed for the proposed structure.
A New Proposal for OFCC-based Instrumentation Amplifier Deva Nand; Neeta Pandey
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 1: February 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (775.767 KB) | DOI: 10.11591/ijece.v7i1.pp134-143

Abstract

This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors.  The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
Co-Authors Deva Nand Gurumurthy Komanaplli Rajeshwari Pandey