Basma M. K. Younis
Northern Technical University

Published : 2 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 2 Documents
Search
Journal : TELKOMNIKA (Telecommunication Computing Electronics and Control)

Comparative performance of optical amplifiers: Raman and EDFA Khalis A. Mohammed; Basma M. K. Younis
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 18, No 4: August 2020
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v18i4.15706

Abstract

The in-line optical signal amplification is often used in optical communication systems to accomplish longer transmission distances and larger capacity. In this proposed paper, the operation of two types of optical amplifiers for 16×10 Gbps wavelength division multiplexing system had been examined by changing transmission distance from 10 to 200 km with a dispersion equals to 16.75 ps/nm/km. The analysis and design of such systems ordinarily includes many signal channels, nonlinear devices, several topologies with many noise sources, is extremely complex and effort-exhaustive. Therefore, theoretical studies with simulation CAD software of systems are become necessity to predict and optimize system performance. The comparison between EDFA and Raman has already explored by many researchers in varying ways in this work and to achieve obove objectives, the OptiSystem software was used to design the proposed fiber optic communications system and to simulate results. Performance for the present system was evaluated for parameters like bit error rate (BER), quality factor (QF), total gain with eye opening factor. It was saw that EDFA provides better results, in the maximal transmission distance 64% better than Raman amplifier, 57.5% for gain and 26.7% for maximum quality factor. As a future study a hybrid amplifier can produce better quality of amplification.
Hardware accelerator for anti-aliasing Wu's line algorithm using FPGA Basma M. K. Younis; Ahmed Kh. Younis
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 19, No 2: April 2021
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v19i2.18158

Abstract

Digital images are suffering from the stair-step effect because they are built from small pixels. This effect termes aliasing and the method uses to decrease so-called anti-aliasing. This paper offers a hardware accelerator of an anti-aliasing algorithm using HLS (high level synthesis) along straight-line segments or edges. These straight-line segments are smoothed by modifying the intensity of the pixel. The hardware implementation of two different architectures which is based on Zynq FPGA are presented in this work. The first architecture is built from one core while the second architecture is built from multi-core and uses a parallel technique to speed up the algorithm by dividing line segments into sub-segments and drawing them after smoothing instantaneously to formulate the main line. This parallel usage leads to a very fast execution of Wu's algorithm which is represented one-tenth hardware runtime for one core only. Also, the optimized resource utilization and power consumption for different cores have been compared, through single-core design which utilizes 8% and consumes 1.6 W, while utilized resources using 10 cores are 77% with a power consumption of 2 W.