Garuda - Garba Rujukan Digital

p-Index From 2020 - 2025

P-Index

This Author published in this journals

All Journal Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics

Sasilatha T.

AMET University

Author-ID : 2460617

Computer Science & IT Electrical & Electronics Engineering Engineering

Published : 6 Documents Claim Missing Document

Claim Missing Document

Articles

Title

Wireless Network For Strategic Boundary Supervision System Anu Priya; Sasilatha T.
Bulletin of Electrical Engineering and Informatics Vol 6, No 4: December 2017
Publisher : Institute of Advanced Engineering and Science

The major trouble with national security is "Terrorism" happening in borders. In border areas, regular forces or even satellites cannot monitor accurately intruding. The wireless sensor network scheme gives a possible way to explain this issue. To outline a wireless remote system of estimated sensor motes that contains various installed sensors and a processor to detect and impart an adversary interruption crosswise over a border and war zones. The idea is to distribute many smartdust motes inside an enormous geological region. Every one of these motes shapes a remote system, and one of them will go about as the system organiser that can control the whole system and furthermore goes about as a passage to the outside world. The preferred standpoint with these little motes is that it can be conveyed in a couple of hours by a pair of men or even dropped from an airborne helicopter. Every mote comprises of an assortment of sensors to distinguish every single potential type of interruption.

System on Chip Based RTC in Power Electronics R. Dorothy; Sasilatha T.
Bulletin of Electrical Engineering and Informatics Vol 6, No 4: December 2017
Publisher : Institute of Advanced Engineering and Science

Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

Co-Authors Anu Priya R. Dorothy

Title Search

Found 2 Documents Search Journal : Bulletin of Electrical Engineering and Informatics

Abstract

Abstract

Title

Found 2 Documents
Search
Journal : Bulletin of Electrical Engineering and Informatics