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Archana Rani
Manav Rachna International University
Computer Science & IT Electrical & Electronics Engineering Engineering

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Journal : Bulletin of Electrical Engineering and Informatics

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An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM Archana Rani; Naresh Grover
Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (822.571 KB) | DOI: 10.11591/eei.v7i2.818

Abstract

This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route & Placed design.
Co-Authors Naresh Grover