<![CDATA[A 4 GHz PLL (phase-locked loop)-type frequency synthesizer has been implemented in the standard 0.18μm mixed-signal and RF 1P6M CMOS technology. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detailed. The measured results show that the locked range was 4096-4288 MHz and the phase noise could reach -117 dBc/Hz at 1MHz offset from the carrier 4.154 GHz, the output power is about -3 dBm. The chip area is 0.675 mm×0.700 mm. The DC power consumption of the core part is about 24 mW under 1.8 V supply. DOI: http://dx.doi.org/10.11591/telkomnika.v11i2.2003]]>
