Article Per Year (5 Year)
p-Index From 2021 - 2026
0.23
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering
Vivek Raj Kempanna
Dayananda Sagar College of Engineering
Computer Science & IT Electrical & Electronics Engineering

Published : 1 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 1 Documents
Search
Journal : International Journal of Electrical and Computer Engineering

 1 
Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis Vivek Raj Kempanna; Dinesha Puttaraje Gowda
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 6: December 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i6.pp6332-6340

Abstract

The IEEE 802.15.4 physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters.
Co-Authors Dinesha Puttaraje Gowda