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Bukya Balaji
Koneru Lakshmaiah Educational Foundation
Computer Science & IT Electrical & Electronics Engineering

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Journal : International Journal of Electrical and Computer Engineering

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Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor Padakanti Kiran Kumar; Bukya Balaji; Karumuri Srinivasa Rao
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 3: June 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i3.pp3519-3529

Abstract

In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10-17 farads and 1.11x10-12 seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.
Co-Authors Karumuri Srinivasa Rao Padakanti Kiran Kumar