Article Per Year (5 Year)
p-Index From 2021 - 2026
0.408
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering
Khumsat, Phanumas
Unknown Affiliation
Computer Science & IT Electrical & Electronics Engineering

Published : 2 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 2 Documents
Search
Journal : International Journal of Electrical and Computer Engineering

 1 
Single-phase binary phase-shift keying, quadrature phase shift keying demodulators using an XOR gate as a phase detector Kaewmunee, Apinut; Khumsat, Phanumas
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6092-6101

Abstract

A single-phase/single-loop multiple-phase-shift-keying (m-PSK) demodulator is described. The demodulator relies on a linear range of an exclusive-OR (XOR) gate employed as a phase detector. The phase controller takes the average output from the XOR gate and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for an m-PSK signal. The proposed single-phase binary-/quadrature-PSK (BPSK/QPSK) demodulators have been implemented with low-cost discrete components. The core of the phase controller simply relies on number of stages of a full-wave rectifier and a linear amplifier built from well-known op-amp-based negative feedback circuits. The demodulator prototypes operate from a single supply of 5 V. At a carrier frequency of 100 kHz, both the BPSK and QPSK demodulators achieved the maximum symbol rate of 20 ksymbol/s respectively. At these symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 2×10-10 and 7×10-10.
A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator Chaichomnan, Chutpipat; Khumsat, Phanumas
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6102-6117

Abstract

A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flip-flop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18-mm digital complementary metal–oxide–semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10-10 and 9.8×10-10, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ.
Co-Authors Chaichomnan, Chutpipat Kaewmunee, Apinut