250 MHz Multiphase Delay Locked Loop for Low Power Applications

Shruti Suman (Mody University of Science and technology, Lakshmangarh, Rajasthan, India)
K. G. Sharma (Chandigarh College of Engineering and Technology, Chandigarh, India)
P. K. Ghosh (Mody University of Science and technology, Lakshmangarh, Rajasthan, India)

International Journal of Electrical and Computer Engineering
Vol 7, No 6: December 2017

Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz.