International Journal of Electrical and Computer Engineering
Vol 4, No 6: December 2014

An Area-Optimized Chip of Ant Colony Algorithm Design in Hardware Platform Using the Address-Based Method

E. Shafigh Fard (Najafabad branch, Islamic Azad University)
K. Monfaredi (Azarbaijan Shahid Madani University)
M. H. Nadimi (Najafabad Branch, Islamic Azad University)



Article Info

Publish Date
01 Dec 2014

Abstract

The ant colony algorithm is a nature-inspired algorithm highly used for solving many complex problems and finding optimal solutions; however, the algorithm has a major flaw and that is the vast amount of calculations and if the proper correction algorithm and architectural design are not provided, it will lead to the increasing use of hardware platform due to the high volume of operations; and perhaps at higher scales, it causes the chip area not to work because of the high number of problems; hence, the purpose of this paper is to save the hardware platform as far as possible and use it optimally through providing a particular algorithm running on a reconfigurable chip driven by the address-based method, so that the comparison of synthesis operations with the similar works shows significant improvements as much as 1/3 times greater than the other similar hardware methods.DOI:http://dx.doi.org/10.11591/ijece.v4i6.6923

Copyrights © 2014






Journal Info

Abbrev

IJECE

Publisher

Subject

Computer Science & IT Electrical & Electronics Engineering

Description

International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of ...