International Journal of Electrical and Computer Engineering
Vol 10, No 2: April 2020

Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors

Ajay Kumar Singh (University Melaka Malaysia)
Tan Chun Fui (University Melaka Malaysia)
Tan Wee Xin Wilson (University Melaka Malaysia)



Article Info

Publish Date
01 Apr 2020

Abstract

In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 1016 /cm3. The higher concentration in the source (Ns) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.

Copyrights © 2020






Journal Info

Abbrev

IJECE

Publisher

Subject

Computer Science & IT Electrical & Electronics Engineering

Description

International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of ...