FPGA Implementation of a 64-Bit RISC Processor Using VHDL

Imran Mohammad (QIS College of Engineering, Andhra Pradesh)
Ramananjaneyulu K (QIS College of Engineering, Andhra Pradesh)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 1, No 2: July 2012

In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.