BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

M. Parvathi (ECE Dept, BVRIT, Hyderabad, Telangana, India)
N. Vasantha (ECE Dept, BVRIT, Hyderabad, Telangana, India)
K. Satya Prasad (ECE Dept, BVRIT, Hyderabad, Telangana, India)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 7, No 1: March 2018

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.