FPGA Implementation of High Speed Hardware Efficient Carry Select Adder

Saravanakumar Saravanakumar (Anna University, Department of ECE Bannari Amman Institute of Technology, Tamil Nadu, India)
Vijeyakumar Vijeyakumar (Anna University, Dr. Mahalingam College of Engg & Technology, Tamil Nadu, India)
Sakthisudhan Sakthisudhan (Anna University, Adhi College of Engg & Technology, Tamil Nadu, India)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 7, No 1: March 2018

This paper presents a novel architecture for high speed and hardware efficient carry select  addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.