High Speed Area Efficient FPGA Implementation of AES Algorithm

P. B. Mane (AISSMS Inst. Of Information Technology)
A. O. Mulani (AISSMS Inst. Of Information Technology)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 7, No 3: November 2018

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.