International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 3, No 2: July 2014

Design of AES Algorithm for 128/192/256 Key Length in FPGA

Pravin V. Kinge (G. H. Raisoni College of Engineering)
S.J. Honale (G. H. Raisoni College of Engineering)
C.M. Bobade (G. H. Raisoni College of Engineering)



Article Info

Publish Date
01 Jul 2014

Abstract

The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. The available AES algorithm is used forĀ  data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to AES algorithm, to obtain the encrypted image. and the encrypted image is the input to AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit AES algorithm for data encryption and decryption, also to compare the speed of operation, efficiency, security and frequency . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language (VHDL).

Copyrights © 2014






Journal Info

Abbrev

IJRES

Publisher

Subject

Economics, Econometrics & Finance

Description

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component ...