Survey on Performance and Energy consumption of Fault Tolerance in Network on Chip

B. Naresh Kumar Reddy (National Institute of Technology Goa)
Vasantha M.H (National Institute of Technology Goa)
Nithin Kumar Y.B. (National Institute of Technology Goa)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 5, No 1: March 2016

Network on Chip (NoC) is a communication subsystem, which has the logic for sending and receiving the data from different sources in a single IC, is adopting the technology of VLSI making it to be as compact as possible. However, the increasing probability of failures in NoC’s has been raising concern among the researchers due to large scale integration of components. In specific the issues of fault-tolerance, increase in length of global wires of NoC has to be addressed for on chip and multi core architectures. This survey presents a perspective on existing NoC Fault-tolerant algorithm and a Corresponding distributed fault analysis strategy that encourages in observing the fault status of individual NoC components and their adjacent communication links. The analysis of the Fault-tolerant Network subjected to dynamic workloads for large scale applications is also equally important. This research paper mainly emphasizes on Fault tolerant NoC strategies summarizing over thirty research papers.