A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW

B. Naresh Kumar Reddy (NIT Goa)
N. Suresh (K.L.University)
J.V.N. Ramesh (K.L.University)

International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 5, No 3: November 2016

Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.