International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol 8, No 1: March 2019

Verilog based efficient convolution encoder and viterbi decoder

Md. Abdul Rawoof (MLR Institute of Technology)
Umasankar Ch. (MLR Institute of Technology)
D. Naresh Kumar (MLR Institute of Technology)
D. Khalandar Basha (Institute of Aeronautical Engineering)
N. Madhur (Unknown)



Article Info

Publish Date
11 Feb 2019

Abstract

In the today’s digital communication Systems, transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

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Journal Info

Abbrev

IJRES

Publisher

Subject

Economics, Econometrics & Finance

Description

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component ...