Bulletin of Electrical Engineering and Informatics
Vol 8, No 2: June 2019

Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

Cardarilli, Gian Carlo (Unknown)
Nunzio, Luca Di (Unknown)
Fazzolari, Rocco (Unknown)
Giardino, Daniele (Unknown)
Matta, Marco (Unknown)
Re, Marco (Unknown)
Spanò, Sergio (Unknown)
Simone, Lorenzo (Unknown)

Article Info

Publish Date
01 Jun 2019

Abstract

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.

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Journal Info
Bulletin of Electrical Engineering and Informatics
Website

Abbrev

EEI

Publisher

Universitas Ahmad Dahlan

Subject

Electrical & Electronics Engineering

Description

Bulletin of Electrical Engineering and Informatics (Buletin Teknik Elektro dan Informatika) ISSN: 2089-3191, e-ISSN: 2302-9285 is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the ...