<![CDATA[All digital successive approximation register-controlled delay-lock loops (SAR DLL) are widely used in system-on-chip to solve the clock generation and skew problems for their fast-locking characteristic. However, the conventional SAR DLL has the dead lock problem. So many improved solutions are proposed to solve the dead lock problem. Based on the resettable delay line, improved SAR controller and phase comparator are depicted. By these, a harmonic-free and fast-locking all digital SAR DLL without dead lock is implemented. Post-layout transistor-level simulation results show that the lock-in and relock-in time are both within N cycles of input clock for N-bit SAR controller. The dead lock problem of the conventional SAR DLL is eliminated very well. DOI: http://dx.doi.org/10.11591/telkomnika.v11i4.2341]]>
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