Estimation of power and delay in CMOS circuits using LCT

Pramod kumar Aylapogu (lendi institute of engineering and technology jonnada,vizianagaram,andhrapradesh,india-535005)
B.L.V.S.S Aditya (JNTUK Vizianagaram (A.P.), India)
G. Sony (JNTUK Vizianagaram (A.P.), India)
Ch Prasanna (JNTUK Vizianagaram (A.P.), India)
A Satish (JNTUK Vizianagaram (A.P.), India)

Indonesian Journal of Electrical Engineering and Computer Science
Vol 14, No 2: May 2019

With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors(HTLCT). In this paper, we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The estimation of power and delay will be discussed using LCT’s and HTLCT’s