An efficient hardware logarithm generator with modified quasi-symmetrical approach for digital signal processing

Minh-Hong Nguyen (Le Quy Don Technical University)

International Journal of Electrical and Computer Engineering
Vol 10, No 5: October 2020

This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.