<![CDATA[To reduce the effects of single-event upsets (SEUs) on field-programmable gate arrays (FPGAs), we propose anti-VPR, an anti-SEU algorithm. The Anti-VPR algorithm is based on VPR, a popular placement and routing tool. The proposed algorithm optimizes the FPGA place cost function and reduces the occurrence of errors, such as open circuit error and short circuit error, by computing the error propagation probability and node error rate of the Configurable Logic Blocks. The Anti-VPR algorithm is implemented and tested on several MCNC benchmark circuits. Experimental results show that the proposed Anti-VPR algorithm achieves a 36.2% greater reduction of sensitive bits compared with the original VPR algorithm without the need for extra hardware overhead, unlike the traditional TMR approach.]]>
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