Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

Kanan Bala Ray (KIIT UNIVERSITY)
Sushanta Kumar Mandal (Centurion University of Technology and Management)
Shivalal Patro (KIIT UNIVERSITY)

Indonesian Journal of Electrical Engineering and Computer Science
Vol 4, No 2: November 2016

In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell