A Low Quiescent Current Fast Settling Capacitor-less Low Drop Out Regulator Employing Multiple Loops

Suresh Alapati (National Institute of Technology)
Patri Sreehari Rao (National Institute of Technology)

Indonesian Journal of Electrical Engineering and Computer Science
Vol 10, No 3: June 2018

This paper presents a fast transient and low noise capacitor-less LDO using multiple loops. The proposed LDO exploits adaptive biasing, bulk modulation and a fast reacting control loop for achieving high performance striking reasonable tradeoffs among quiescent current, transient response and stability. The proposed LDO offers a load regulation of 0.095µV/mA while consuming quiescent current of 16 µA. It exhibits a load transient of 134.23mV with a settling time of 240.8ns against 0 to 100mA load variation with 40pF output capacitor. It exhibits an integrated noise of 31.027 pV2 /Hz at 10 Hz for a maximum load current of 100mA. The proposed LDO is designed using 0.18-µm 1P6 CMOS process.